The circuit diagram of the NOR gate flip-flop is shown in the figure below:Ī simple one bit RS Flip Flops are made by using two cross-coupled NOR gates connected in the same configuration. The RS flip-flop is said to be in an invalid condition if both the set and reset inputs are activated simultaneously. The bistable RS flip flop is activated or set at logic “1” applied to its S input and deactivated or reset by a logic “1” applied to R. This unstable condition is known as Meta- stable state. The flip-flop switches to one state or the other and any one output of the flip-flop switches faster than the other. This unstable condition arises when the LOW input is switched to HIGH. The flip-flop goes to an unstable state as both the output goes LOW. When the input state R = 0 and S = 0 is an invalid condition and must be avoided because this will give both outputs Q and Ǭ at logic level “1” at the same time and the necessary condition is that Q to be the inverse of Ǭ. The truth table of the Set/Reset is given below: Stateįrom the truth table, it is clear that when both the inputs S = 1 and R =1 the outputs Q, and Ǭ can be at either logic level ‘1’ or “0” depending upon the state of the inputs. Therefore, the flip-flop circuits “RESET” state has been latched. If the set input S now changes the state to logic “1” with the input R remaining at logic “1”, the output Q still remains LOW at logic level “0”. The output Q is fed to input B, so both the inputs to NAND gate Y are at logic “1”., therefore, Q = 0. As gate X has one of its inputs at a logic “0” its output Q must equal logic level “1”. In this second stable state, Q is at logic level ‘0” and its inverse output Q is at logic level “1”. Therefore, the flip-flop circuit is said to be “LATCHED” or “SET” with Q = 1 and Ǭ = 0. The output at Q remains at HIGH or at logic level “1” as one of its inputs is still at logic level “0”.Īs a result, there is no change in state. The NAND gate Y input are now (R = 1) and (B = 0). The reset input R changes its state, and goes HIGH to logic “1” with S constant at logic “1”. Both the inputs of the NAND gates X are at logic “1”, and therefore, its output Q must be at the logic level”0”. The Output (Q) is fed back to the input “A”. Therefore, its output Q must be at a logic level “1” (NAND gate principles). If the input R is at logic level “0” (R = 0) and input S is at the logic “1” (S = 1), the NAND gate Y has, at least, one of its inputs at a logic “0”.
The two outputs are Q and Q bar as shown in the figure below:Ĭonsidering the above circuit. The device consists of two inputs one is known as SET, (S) and the other is called as RESET, (R). The feedback is fed from each output to one of the other NAND gate input. It forms Set/Reset bi-stable or an active LOW RS NAND gate latch. The symbol of the RS Flip-Flop is shown below:Ī pair of cross-coupled 2 unit NAND gates is the simplest way to make any basic one-bit set/reset RS Flip Flop. The RS Flip Flop actually has three inputs, SET, RESET and its current output Q relating to its current state. The basic NAND gate RS Flip Flop circuit is used to store the data and thus provides feedback from both of its outputs again back to its inputs. Flip flop word means that it can be “FLIPPED” into one logic state or “FLOPPED” back into another. It depends upon the set/reset condition of the flip-flop. The flip-flop is reset back to its original state with the help of RESET input and the output is Q that will be either at logic level “1” or logic”0”. It has two inputs, one is called “SET” which will set the device (output = 1) and is labelled S and another is known as “RESET” which will reset the device (output = 0) labelled as R.
The Flip Flop is a one-bit memory bi-stable device. The RS Flip Flop is considered as one of the most basic sequential logic circuits. In this article, RS Flip Flop is explained in detail. There are two types of flip flop one is RS Flip Flop and JK Flip Flop.
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